Memory devices are formed for various purposes including, for example, internal storage areas in computers, personal media players, cameras, and other electronic devices. The term, “memory” identifies data storage that typically comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. One type of memory cell utilizes transistors capable of storing a charge. Such transistors typically comprise a pair of diffusion regions, referred to as a source and a drain, spaced apart and within a semiconductor, for example, a semiconductive substrate, such as a bulk single crystal silicon wafer. The transistors also include a gate provided adjacent to the semiconductor and between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions.
FIG. 1 is a schematic view of an example of a NAND Flash memory device 100. As shown, the memory device 100 includes a plurality of active areas 110 forming an array, each active area 110, extending longitudinally along a substrate 120 and separated from each other by isolation regions 130 (e.g., shallow trench isolation (STI) regions). The active areas 110 comprise a plurality of diffusion regions at least in regions between access lines, which are commonly referred to as wordlines, such as wordlines 140. Wordlines 140 extend across a plurality of the active areas 110 and comprise control gates. The wordlines 140 are grouped together in blocks that typically comprise thirty-two (32) wordlines, although only five (5) wordlines are shown in each of the two blocks illustrated in FIG. 1 due to space limitations. On one side of each block is a gate 140′ configured as a drain select line, and on another side of each block is a gate 140″ configured as a source select line, each of which is configured to select a block of wordlines for reading from and writing to the memory device 100. A source slot 165 can be at one end of a block and a plurality of data line contacts, such as bit contacts 170, are at an opposing end of each block. The bit contacts 170 are coupled to the active areas 110 and to a data line, such as bitline 180, of a plurality of data lines.
Use of conventional processes to form a memory device, such as that shown in FIG. 1, may result in an increase in the width of the diffusion regions at an end thereof that is proximal to the surface of the substrate 120. For example, FIG. 2 illustrates a partial cross-sectional view of the memory device 100 of FIG. 1 taken along a portion of section line 2-2 and showing a plurality of active areas 110 of the memory device 100 coupled to bit contacts 170. As discussed above, each of the active areas 110 of the plurality of active areas 110 is electrically isolated from other active areas 110 by isolation regions, such as shallow trench isolation (STI) regions 130 between the active areas 110. The active areas 110 have a width 210 at a depth (e.g., about 30-40 nanometers or more) from the surface of the substrate 120. However, conventional active areas 110 may also include a diffusion region comprising an end 220 proximate the active surface of the substrate 120 having a width 230 that is larger than the width 210 of the active area 110. Such an increase in width may be caused by, for example, unintended nucleation and growth of new crystals in the semiconductor material, and typically occurs during the manufacturing process.
The increase in width between widths 210 and 230 in the end 220 of the active areas 110 proximate the active surface of the substrate 120 may also be referred to in this disclosure as a “mushroom” or “mushrooming.” As used herein the term “mushroom” or “mushrooming” is intended to describe the nucleation and growth of new crystals in diffusion regions of a single crystal semiconductor substrate resulting in enlargement in width of the diffusion regions. Mushrooming becomes problematic as semiconductor devices are scaled to increasingly smaller dimensions. For example, the increase in width associated with the so-called “mushroom” can result in short circuits between active areas 110 that are typically separated by STI regions 130, and present an obstacle in reducing the pitch between active areas in relation to reducing the overall size of semiconductor devices.